Latest Articles for Hardware Design

Exploring new methods in channel estimation to improve wireless communication accuracy.

A new approach improves deep learning simulation in hardware design.

Comparing AMD/Xilinx Versal ACAP and Intel Stratix 10 NX in deep learning tasks.

New computing approach boosts performance and efficiency in embedded systems.

Exploring methods to assess program reliability on fast, small chips.

New algorithms improve circuit designs for faster calculations.

Learn how chiplet technology is reshaping AI hardware design for better efficiency.

A new method enhances detection of microarchitectural vulnerabilities in computer systems.

New methods improve efficiency in digital circuit design using ACD.

A new model enhances design quality prediction in hardware development.

A new framework improves the processing of convolutional neural networks on limited-resource devices.

This article assesses the effectiveness of large language models in creating hardware assertions.

A new instruction set boosts performance in data streaming tasks.

A new framework enhances C/C++ code compatibility for hardware synthesis.

A new method enhances HDL code generation accuracy using LLMs.

MaskedHLS offers a solution for building secure hardware protecting against power side-channel attacks.

A new algorithm streamlines modulus operations, beneficial for cryptography and prime calculations.

New methods improve efficiency in deep neural networks, reducing energy use and increasing speed.

An overview of key issues in designing specialized computing hardware.

AutoVCoder enhances LLMs' ability to generate high-quality Verilog code effectively.

A new framework improves RTL code generation through dataset augmentation and self-reflection.

A new approach enhances energy efficiency and processing speed in CNNs.

Using FPGAs and HLS tools to enhance FTLE calculations in fluid dynamics.

A study reveals vulnerabilities in logic locking affecting data security.

VerilogCoder uses AI to simplify and improve hardware design tasks.

Learn how dynamic techniques improve hardware performance and adaptability.

Exploring the integration of LLMs in High-Level Synthesis for effective hardware creation.

A new benchmark assesses LLMs’ ability to generate Verilog code.

Takum arithmetic offers improved precision and efficiency over traditional systems.

Innovative architecture enhances efficiency in deep learning through optical computation.

A new framework enhances neural network processing for scientific research.

AIvril enhances RTL code generation through automated syntax checking and functional verification.

qSAT solver utilizes quantum methods for efficient hardware design verification.

A new approach improves hardware circuit design using machine learning.

Exploring low-power spintronic neurons for efficient AI computing.

New methods in turbo equalization improve signal reception and reduce complexity.

New design improves reliability and security for IoT devices using PUF technology.

A new approach enhances deep learning model performance amidst noise.

Optimizing DNNs with power-of-two quantization for resource-limited devices.

FPGAs offer flexibility but introduce significant security risks that need to be addressed.