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# Computer Science# Hardware Architecture

Improving Task Management in Mixed-Criticality Systems

A new framework enhances responsiveness in systems handling varied task priorities.

― 6 min read


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In today's technology landscape, there is a growing need for systems that can efficiently handle complex tasks while ensuring that critical functions remain reliable. These systems, known as Mixed-criticality Systems (MCSs), are designed to manage tasks with different levels of importance. For example, in a car, a system might prioritize safety functions, like collision avoidance, while still managing less critical functions, like entertainment options.

Modern MCSs often use a mix of different types of hardware to get the job done, which can help meet increasing demands for computational power. However, many of these systems face challenges when it comes to effectively managing tasks based on their importance. This article will discuss a new approach designed to tackle these issues, focusing specifically on how to improve the performance of hardware components used in MCSs.

Background

MCSs must handle tasks that vary in their criticality. High-criticality tasks require prompt execution to maintain safety and function, while lower-criticality tasks can tolerate delays. Many of these systems employ specialized hardware, such as deep neural network (DNN) accelerators, to speed up computation. However, this hardware often struggles with task prioritization.

One significant issue that arises is the occurrence of priority inversions. This happens when low-priority tasks take up system resources, causing high-priority tasks to wait longer than necessary. Such delays can lead to serious problems, especially in safety-critical applications. For example, in an automotive system, a delay in processing collision avoidance data can have life-threatening consequences.

The Problems

One of the main challenges in MCSs is that many hardware components are built for high throughput instead of efficient task switching. This means that tasks are often processed in a way that does not allow for high-priority tasks to interrupt ongoing low-priority tasks. This leads to long periods where important tasks are left waiting.

To address these issues, some researchers have looked into splitting workloads across different systems or utilizing software solutions that modify how tasks are managed. However, making these adjustments often requires significant changes to both the hardware and software, which can be time-consuming and expensive.

A New Approach: MESC

To overcome these challenges, we propose a new framework called Make Each Switch Count (MESC). The goal of MESC is to provide a more efficient way to switch between tasks at a much finer level of granularity, allowing for immediate reaction to high-priority tasks without needing to completely stop ongoing lower-priority tasks.

Key Features of MESC

  1. Instruction-Level Preemption: MESC allows for tasks to be interrupted at the level of individual instructions, instead of only at the end of entire algorithms. This greatly reduces the waiting time for high-priority tasks.

  2. Coherent System Structure: MESC integrates both hardware and software changes to create a cohesive system that can handle multiple tasks effectively. This means designing a new accelerator that works well with existing hardware and software components but improves how tasks are managed.

  3. Theoretical Validation: Along with the practical implementation, MESC includes a theoretical model that helps ensure that the new methods are reliable and predictable in their behavior.

The Hardware Component: DNN Accelerators

DNN accelerators are specialized pieces of hardware designed to perform complex computations quickly, making them ideal for tasks such as image recognition and natural language processing. However, their design often makes them difficult to integrate with traditional task management systems.

Gemmini Architecture

One example of a DNN accelerator is the Gemmini architecture. It uses a systolic array, which is a type of grid of processors that communicate with each other to perform calculations. Gemmini is designed to work alongside general-purpose CPUs, allowing for parallel processing. But its design is primarily focused on maximizing throughput rather than on task switching.

MESC introduces a method to make Gemmini more adaptable, allowing it to preempt tasks at the instruction level. This means that when a high-priority task arrives, it can interrupt the current processes, thereby enhancing system responsiveness.

The Software Component: Operating System Integration

Along with hardware improvements, MESC also includes modifications to the operating system (OS). These modifications help the OS effectively manage task switching and resource allocation.

Task Scheduling

A critical feature in MESC is a new scheduler designed to efficiently manage tasks. The scheduler constantly monitors the system's status and decides when to interrupt a task. When a high-priority task needs immediate action, the scheduler can quickly implement a context switch, allowing the important task to run while keeping track of what the previous task was doing.

Task Monitoring

Another important aspect is a task monitor that tracks the current state and resource needs of each task. This component ensures that the system maintains accurate information about all tasks, making it easier to manage context switches and resource allocation effectively.

Experimental Results

To demonstrate the effectiveness of MESC, a series of tests were conducted using an AMD Alveo U280 FPGA board. The tests involved a variety of DNN workloads to evaluate the performance of the new system.

Testing Context Switching

One of the primary focuses was to assess how well MESC could handle context switching and the overhead associated with it. The results showed significant improvements in both the time taken to save and restore task states compared to traditional methods. In particular, MESC was able to reduce the duration of critical waiting periods from millions of cycles to just hundreds, making it far more efficient.

Successful Task Execution

The success of task execution under MESC was also evaluated. Tests showed that even when system utilization was high, the new framework maintained a high success rate, meaning that tasks were more likely to meet their deadlines. In scenarios without the context-switching capabilities of MESC, the success rate dropped dramatically when system load increased.

Future Applications

The improvements brought by MESC could have far-reaching implications for various industries. For instance, in automotive systems, the ability to manage tasks more effectively could lead to safer autonomous vehicles. Similarly, in aerospace and medical technologies, ensuring that critical tasks are prioritized can have significant safety benefits.

Expansion Beyond DNNs

While this framework has been applied to DNN accelerators, the principles outlined can be adapted to other types of co-processors as well. This flexibility means that MESC could potentially improve the performance of a wide range of systems beyond just those dealing with machine learning tasks.

Conclusion

MESC offers a promising new approach to managing mixed-criticality systems, addressing critical issues related to task prioritization and responsiveness. By integrating hardware and software solutions, MESC enhances task management capabilities, significantly reducing the waiting times for high-priority tasks while maintaining overall system efficiency.

As technology continues to evolve, frameworks like MESC will become increasingly vital for ensuring that complex systems can operate safely and effectively under a variety of conditions.

Original Source

Title: MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs

Abstract: Modern Mixed-Criticality Systems (MCSs) rely on hardware heterogeneity to satisfy ever-increasing computational demands. However, most of the heterogeneous co-processors are designed to achieve high throughput, with their micro-architectures executing the workloads in a streaming manner. This streaming execution is often non-preemptive or limited-preemptive, preventing tasks' prioritisation based on their importance and resulting in frequent occurrences of algorithmic priority and/or criticality inversions. Such problems present a significant barrier to guaranteeing the systems' real-time predictability, especially when co-processors dominate the execution of the workloads (e.g., DNNs and transformers). In contrast to existing works that typically enable coarse-grained context switch by splitting the workloads/algorithms, we demonstrate a method that provides fine-grained context switch on a widely used open-source DNN accelerator by enabling instruction-level preemption without any workloads/algorithms modifications. As a systematic solution, we build a real system, i.e., Make Each Switch Count (MESC), from the SoC and ISA to the OS kernel. A theoretical model and analysis are also provided for timing guarantees. Experimental results reveal that, compared to conventional MCSs using non-preemptive DNN accelerators, MESC achieved a 250x and 300x speedup in resolving algorithmic priority and criticality inversions, with less than 5\% overhead. To our knowledge, this is the first work investigating algorithmic priority and criticality inversions for MCSs at the instruction level.

Authors: Jiapeng Guan, Ran Wei, Dean You, Yingquan Wang, Ruizhe Yang, Hui Wang, Zhe Jiang

Last Update: 2024-09-23 00:00:00

Language: English

Source URL: https://arxiv.org/abs/2409.14837

Source PDF: https://arxiv.org/pdf/2409.14837

Licence: https://creativecommons.org/licenses/by/4.0/

Changes: This summary was created with assistance from AI and may have inaccuracies. For accurate information, please refer to the original source documents linked here.

Thank you to arxiv for use of its open access interoperability.

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