Temperature Effects on Molybdenum Disulfide Transistors
This study examines how temperature impacts hysteresis in MoS FETs.
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Table of Contents
The world of electronics is rapidly changing with the advent of new materials that can improve device performance. One such material is molybdenum disulfide (MoS), which is a type of transition metal chalcogenide. It can be used to build transistors that are smaller, faster, and more energy-efficient than traditional silicon-based devices. However, as with any new technology, there are challenges that need to be addressed before these devices can be widely used.
In MoS transistors, a significant issue arises from interface Traps. These traps can capture and release charge carriers, leading to problems such as reduced mobility of these carriers, increased response time, and unwanted noise. This study investigates how temperature affects the behavior of these traps in MoS field-effect transistors (FETs), particularly focusing on the reduction of hysteresis with cooling.
Experimental Setup
To study the behavior of MoS FETs, a specific method was used to create the devices. MoS layers were transferred onto silicon oxide (SiO) substrates. This process involved using a sticky film to lift MoS layers from their original location and placing them onto the target substrate. The successful transfer was confirmed using optical imaging and Raman spectroscopy, which allowed for the identification of the number of layers present in the MoS devices.
Once the MoS was in place, gold contacts were added to create the necessary electrical connections. These contacts were formed using a technique that ensures good electrical properties without the contamination often caused by traditional processes. After assembly, electrical measurements were taken from the devices, particularly focusing on how the conductive properties change as temperature varies.
Understanding Hysteresis
Hysteresis refers to the lag between an input and output in a system. In the case of MoS FETs, when the gate voltage is changed, the device does not react instantaneously; instead, it takes some time for the charge carriers to stabilize, leading to a difference between the forward and backward voltage values. This behavior can lead to complications in device performance.
The focus of this study is to understand how this hysteresis can be influenced by temperature. When cooled, the behavior of the traps that affect this hysteresis changes, leading to an improvement in how the devices operate. This behavior resembles that seen in certain magnetic materials, where changes occur at specific Temperatures.
Impact of Temperature
The research found that as the temperature decreased, the hysteresis in the MoS FETs became less pronounced. This phenomenon was most notable near a specific temperature, around 225 K. At this point, the dynamics of how the traps behaved changed significantly. Essentially, a blocking effect occurred, where traps became less responsive, leading to a reduction in hysteresis.
When the temperature was lowered to 80 K, the devices showed almost no hysteresis. This allows for more precise control of the voltage needed to switch the devices on and off, which is essential for reliable operation.
Charge Dynamics in MoS FETs
The charge stored in the traps plays a crucial role in how the transistors operate. By controlling the temperature and the gate voltage, it was possible to program the traps to hold specific charge states. This offers a method to control the threshold voltage needed for the device to conduct, providing a versatile way to fine-tune the performance of the transistors.
The findings suggest that the interface traps behave in a complex manner, influenced by both temperature and the state of the traps. Understanding these interactions is important for improving device design and functionality.
The Role of Interface Traps
Interface traps arise due to imperfections at the boundary between different materials, such as MoS and SiO. These traps can capture charge carriers, which can lead to various issues, such as increased noise and fluctuation in conductivity. The dynamics of these traps, particularly how they respond to changes in voltage and temperature, have a significant impact on the performance of MoS FETs.
When a voltage is applied to the gate of the FET, it influences the carriers in the channel as well as the traps. The relationship between the traps and the channel is dynamic; as the gate voltage is varied, the traps can either fill with charge or release it, depending on their energy states relative to the channel's chemical potential.
Simplified Model of Trap Dynamics
The behavior of traps can be modeled to understand their effects on device performance. By simplifying this model, one can explore how the traps affect the flow of charge in the channel. Fast traps respond quickly to changes in voltage, while slow traps take longer to react. This distinction is crucial for understanding hysteresis.
In a typical scenario, the fast traps will equilibrate quickly, meaning they reach a state of balance soon after the gate voltage is adjusted. On the other hand, the slow traps can take much longer to respond, leading to the hysteresis observed in the device measurements. As temperature decreases, the occupancy of these traps becomes less mobile, further influencing the overall device characteristics.
Time-Dependent Responses
When examining how the charge in the traps changes over time, it becomes clear that the initial response is quick, but as time goes on, the slow traps start to adjust their occupancy. This can lead to more complex behavior, as the changes in channel conductance are not simple and instantaneous.
Rather than fitting into a neat exponential decay model, the relaxation of trap occupancy can show a stretched exponential behavior. This pattern indicates that multiple processes are happening at once, with traps responding at differing times.
Hysteresis and Blocking Transition
As previously mentioned, hysteresis decreases as temperature drops. This has practical implications for device use, as less hysteresis leads to more predictable performance. The transition from a hysteretic state to a non-hysteretic state resembles behaviors seen in magnetic materials at certain temperatures.
This understanding of hysteresis can help guide the design of better FETs. By incorporating knowledge of how traps behave at different temperatures and voltages, engineers can develop transistors that are more efficient and reliable.
Experimental Observations
Measurements taken at room temperature showed significant hysteresis in the transfer characteristics of the MoS FETs. As the gate voltage was cycled through various ranges, the differences in voltage required to switch the devices on and off became apparent. At room temperature, there were pronounced differences in the voltage thresholds.
When the temperatures were reduced, particularly below 225 K, the changes in hysteresis behavior were more pronounced. Ultimately, at 80 K, the MoS devices exhibited minimal hysteresis and a controllable threshold voltage, which is highly desirable for electronic applications.
Charge Control through Cooling
In practical applications, the ability to control the threshold voltage through cooling is significant. By cooling MoS FETs under specific gate voltages, one can effectively adjust the traps' charge states. This provides a method to 'program' the device, allowing for customized performance based on the application.
This reversible control mechanism offers a unique pathway for tuning the electrical characteristics of MoS-based devices, which could lead to new functionalities in future electronic systems.
Conclusion
The study of MoS FETs reveals valuable insights into the dynamics of interface traps and how they affect device performance. By understanding how temperature influences hysteresis and charge control, researchers and engineers can work towards designing better, more efficient electronic devices.
This research opens the door to exploring further how new materials can be utilized in electronics, potentially leading to advancements in various fields, including computing and telecommunications. As technology continues to progress, the findings from studies like this one will play a pivotal role in shaping the future of electronic devices.
Title: Blocking transition of interface traps in MoS$_2$-on-SiO$_2$ FETs
Abstract: Electrical conductivity with gate-sweep in a few layer MoS$_2$-on-SiO$_2$ field-effect-transistor shows an abrupt reduction in hysteresis when cooled. The hysteresis and time dependent conductivity of the MoS$_2$ channel are modeled using the dynamics of interface traps' occupancy. The reduction in hysteresis is found to be steepest at a blocking temperature near 225 K. This is attributed to the interplay between thermal and barrier energies and fitted using a distribution of the latter. Further, the charge stored in the blocked traps is programmed at low temperatures by cooling under suitable gate voltage. Thus the threshold gate-voltage in nearly non-hysteretic devices at 80 K temperature is reversibly controlled over a wide range.
Authors: Santu Prasad Jana, Suraina Gupta, Anjan K. Gupta
Last Update: 2023-03-24 00:00:00
Language: English
Source URL: https://arxiv.org/abs/2303.13902
Source PDF: https://arxiv.org/pdf/2303.13902
Licence: https://creativecommons.org/licenses/by/4.0/
Changes: This summary was created with assistance from AI and may have inaccuracies. For accurate information, please refer to the original source documents linked here.
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